It’s nonetheless an especially difficult proposition. “Packaging is not as straightforward as saying, ‘I need to run 100,000 wafers monthly,’” says Jim McGregor, a longtime chip business analyst and the founding father of Tirias Analysis, referring to a steady stream of chips in numerous phases of manufacturing. “It actually comes down to whether or not Intel’s [packaging] fabs could make offers. If we see them increasing these operations extra, that’s an indicator that they’ve.”
Final month, Anwar Ibrahim, the prime minister of Malaysia, revealed in a publish on Fb that Intel is increasing its Malaysian chip-making amenities, which had been first established again in the Nineteen Seventies. Ibrahim mentioned the head of Intel’s Foundry, Naga Chandrasekaran, had “outlined plans to start the first part” of growth, which would come with superior packaging.
“I welcome Intel’s choice to start operations for the advanced later this 12 months,” a translated model of Ibrahim’s publish learn. An Intel spokesperson, John Hipsher, confirmed that it’s constructing out further chip meeting and take a look at capability in Penang, “amid rising world demand for Intel Foundry packaging options.”
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In accordance to Chandrasekaran, who took over Intel’s Foundry operations in 2025 and spoke completely with WIRED throughout the reporting of this story, the time period “superior packaging” itself didn’t exist a decade in the past.
Chips have all the time required some type of integration of transistors and capacitors, which management and retailer vitality. For a very long time the semiconductor business was targeted on miniaturization, or, shrinking the measurement of parts on chips. As the world started demanding extra from its computer systems in the 2010s, chips began to get much more dense with processing items, high-bandwidth reminiscence, and all of the obligatory connective elements. Finally, chipmakers began to take a system-in-packages or package-on-package method, through which a number of parts had been stacked on prime of each other so as to squeeze extra energy and reminiscence out of the similar floor area. 2D stacking gave means to 3D stacking.
TSMC, the world’s main semiconductor producer, started providing packaging applied sciences like CoWoS (chip on wafer on substrate) and, later, SoIC (system on built-in chip) to clients. Basically, the pitch was that TSMC would deal with not simply the entrance finish of chip-making—the wafer half—but in addition the again finish, the place all of the chip tech could be packaged collectively.
Intel had ceded its chip manufacturing lead to TSMC at this level, however continued to spend money on packaging. In 2017 it launched a course of referred to as EMIB, or embedded multi-die interconnect bridge, which was distinctive as a result of it shrunk the precise connections, or bridges, between the parts in the chip package deal. In 2019, it launched Foveros, a sophisticated die-stacking course of. The corporate’s subsequent packaging development was a much bigger leap: EMIB-T.
Introduced final Could, EMIB-T guarantees to enhance energy effectivity and sign integrity between all the parts on the chips. One former Intel worker with direct information of the firm’s packaging efforts tells WIRED that Intel’s EMIB and EMIB-T are designed to be a extra “surgical” means of packaging chips than TSMC’s method. Like most chip developments, this is supposed to be extra energy environment friendly, save area, and, ideally, save clients cash in the lengthy runThe firm says EMIB-T will roll out in fabs this 12 months.
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